Clocked analog delay lines are widely used in discrete time analog signal processing circuits. The delay lines operate to introduce a time lag in a signal, the lag being the time it takes the signal to pass through the line. One type of analog delay line, the conventional bucket brigade, has been particularly preferred since its introduction in the early 1970s due to its relatively simple design, compact topology, and low power consumption requirements.
Despite its benefits, the conventional bucket brigade suffers from at least three significant drawbacks which limit its desirability in modern high-speed integrated circuits. First, its transistors have long settling times, which slow its overall performance. Second, the low output impedance of the transistors can cause signal dependent errors. Finally, the conventional bucket brigade is susceptible to overvoltage conditions which can cause device failures in modern MOS technologies. It is desirable, therefore, to modify a delay line with simple, low-power, small-area circuits that ameliorate such drawbacks.